According to Moore’s law, computers should become faster every two years due to advancements in semiconductor chips. Even though this is what has historically occurred, the evolution’s pace is beginning to slow. Due to advances in artificial intelligence and machine learning, the substantially higher computational ability is now necessary. One approach to overcoming these difficulties is quantum computing, although there are still big obstacles to actualizing scalable quantum computers.
A scaled-up version of a probabilistic computer (p-computer) with stochastic spintronic devices has been created by researchers at Tohoku University, the University of Messina, and the University of California, Santa Barbara (UCSB) for use in challenging computational tasks like combinatorial optimization and machine learning.
A p-computer harnesses naturally stochastic building blocks called probabilistic bits. P-bits oscillate between states, in contrast to bits in conventional computers. A p-computer is a domain-specific computer that can run at room temperature and is used for many machine learning and artificial intelligence applications. P-computers aim to solve complex computing issues in combinatorial optimization and sampling using probabilistic methods, much like quantum computers aim to solve intrinsically quantum problems in quantum chemistry.
In their study, scientists have shown that the p-bits can be efficiently realized using suitably modified spintronic devices called stochastic magnetic tunnel junctions (sMTJ). Only spintronic p-computer proofs-of-concept for combinatorial optimization and machine learning have been shown up to this point, and only on a modest scale.
A photograph of the constructed heterogeneous p-computer consisting of stochastic magnetic tunnel junction (sMTJ) based probabilistic bit (p-bit) and field-programmable gate array (FPGA). ©Kerem Camsari, Giovanni Finocchio, and Shunsuke Fukami et al.
They demonstrated two important Advances:
First, they have demonstrated the compatibility of sMTJ-based p-bits with traditional and programmable semiconductor circuits, specifically Field-Programmable-Gate Arrays (FPGAs). Beyond the preceding small-scale demonstrations, the “sMTJ + FPGA” combination enables considerably bigger networks of p-bits to be constructed in hardware.
Second, in the heterogeneous “sMTJ + FPGA” p-computers, simulated quantum annealing (SQA), a probabilistic simulation of a quantum method, has been carried out with systematic assessments for challenging combinatorial optimization issues.
Additionally, researchers compared the efficiency of p-computers based on sMTJ to that of more traditional computing devices like graphics processing units (GPUs) and tensor processing units (TPUs). They demonstrated that p-computers could significantly outperform conventional technology in terms of throughput and power consumption by leveraging a high-performance sMTJ that a team from Tohoku University had previously developed.
A comparison of probabilistic accelerators as a function of sampling throughput and power consumption. Graphics Processing Units (GPUs) [plotted as N1-N4], Tensor Processing Units (TPUs) [plotted as G1-G2], and simulated annealing machine [plotted as F1] are compared with probabilistic computers, where demonstrated value and projected value are plotted as P1 and P2, respectively. ©Kerem Camsari, Giovanni Finocchio, and Shunsuke Fukami et al.
Professor Shunsuke Fukami, who was part of the research group, said, “Currently, the “s-MTJ + FPGA” p-computer is a prototype with discrete components. In the future, integrated p-computers that use semiconductor process-compatible magnetoresistive random access memory (MRAM) technologies may be possible, but this will require a co-design approach, with experts in materials, physics, circuit design and algorithms needing to be brought in.”
The research group presented ther findings at the 68th International Electron Devices Meeting (IEDM) on December 6th, 2022.